This invention relates to methods of laterally offsetting sidewalls of a trench in a semiconductor substrate relative to sidewalls of overlying structures and structures formed by the same.
Etching in a vertical direction is an integral component of semiconductor processing technology. An isotropic etch employs wet chemicals or reactant gases that etch a material isotropically. The etch rate of isotropic etch processes are difficult to control on a nanoscale, i.e., on a scale from 0.1 nm to 10 nm, because the etch rate is sensitive to temperature and/or supply of etchant.
Plasma processing provides a more precise control of the etch rate. Plasma etch chambers are designed to etch anisotropically in a vertical direction. Advanced semiconductor chips require a high degree of profile control, where the extent of vertical etching may be difficult to control. The ion energy due to the plasma self-bias potential is the ultimately lowest ion energy attainable in plasma reactors, while still enabling a reasonable degree of vertical etching.
Known plasma-etch-based solutions to recessing silicon on a nanoscale generate a post-etch profile in which lateral silicon erosion in the horizontal direction can be up to about ⅓ of the silicon erosion in the vertical direction, i.e., in the direction of the impinging plasma. The amount of lateral etching relative to the depth of a trench formed by a plasma etch is limited. This constraint makes it difficult to enable useful features in semiconductor technology such as tunnel field effect transistor (FET) having strained semiconductor-on-insulator (SSOI) features, which may be a crucial component in obtaining sub-threshold slope characteristics below the classical limit of 60 mV/decade.